Complementary Metal-Oxide-Semiconductor (CMOS) imagers are gaining popularity in the market place. As one skilled in the art understands, CMOS imagers are used to sense light and to provide an electronic representation of the sensed imaged. Accordingly, such devices are useable in digital cameras, to cite just one example.
FIG. 1 shows an example of the basic architecture of a CMOS imager 10 integrated circuit. As can be seen, the CMOS imager 10 includes an array 12 of photosensitive pixels 8 arranged in rows and columns. Read out of a given pixel 8 requires the activation of a given row and column, which is the function of the row decoder circuitry 14 and the column decoder circuitry 16, which in turn are responsive to a row address and column address input into the imager 10. The accessed pixel 8 routes a photo-induced charge from the pixel 8 to its associated column, which meets with column sample-and-hold (CSH) circuitry 18. In FIG. 1, the CSH circuitry 18 is shown at the bottom edge of the pixel array 12 (a bottom-only architecture), although it may also appear at the top and bottom of the array 12 as will be discussed further below. Briefly, the CSH circuit 18 samples the accessed pixel's charge via a sampling capacitor and a reference capacitor (more on this below) to produce signals “sig” and “rst,” which are input to an amplifier 20. The amplifier 20 in turn produces analog signals indicative of the sensed charge, and provides them to an analog-to-digital Converter (ADC) circuit 22 to provide a digital representation of the intensity of the light impingent on the pixel 8 being read.
FIG. 2 shows further details of the pixel array 12 and of the sensing circuitry, and in particular the CSH circuitry 18. As can be seen, each pixel 8 comprises a photodiode 11, which induces a charge which scales in magnitude with the intensity of the light impingent upon the photodiode. This induced charge drives a transfer gate 13 to route some amount of the power supply voltage Vcc onto a given column 15, assuming that the access transistor 17 for the row of the pixel 8 in question has been activated by the row decoders 14. Although not shown, one skilled in the art will realize that each pixel 8 may comprise a reset transistor as well.
The pixel induced charge is thus routed from the column 15 to the CSH circuitry 18, where it is coupled to two capacitors, called the sampling capacitor, Cs 32, and the reference capacitor, Cr 33. As each column has its own dedicated sampling and reference capacitors 32 and 33, they are denoted in conjunction with the column they support: i.e., the capacitors for column 0 are denoted as C0s and C0r. While the actual mechanics for using the sensing and reference capacitors 32 and 33 to sense the induced charge on the pixels 8 are well known and not directly important to embodiments of the invention, it is only briefly explained here. Essentially, a sample signal (“samp_sig”) is sent from the imager 10's control unit (not shown) to close one of transistors 19 move the charge from the column 15 onto the sampling capacitor 32 Cxs. Later in the sensing cycle, the other of the transistors 19 is opened to move charge from the column 15 to the reference capacitor 33 Cxr, which occurs in conjunction with resetting of the pixel. This provides a reference level of charge which is essentially used to normalize the signal charge. The sampled charge on Cxs and the reference charge Cxr are then passed by transistors 21 under control of a column decoder 16 at an appropriate time onto signal lines “sig” and “rst,” which are in turn passed to the amplifier 20 to perform the normalization, and ultimately to the ADC 22 where the magnitude of normalized sensed change is digitized.
Further details concerning the design and operation of CMOS imagers can be found at http://www.olympusmicro.com/primer/digitalimaging/cmosimagesensors.html, a copy of which is submitted in an Information Disclosure Statement filed with this application, and which is hereby incorporated by reference in its entirety.
FIG. 3 shows a typical layout of the sampling and reference capacitors 32 and 33 in conjunction with the pixel array 12. In the embodiment shown, the capacitors 32 and 33 are positioned on both the top and bottom of the array 12 (a top-bottom architecture). So arranged, the top sets of capacitors 32t and 33t service the even-numbered columns, while the bottom sets of capacitors 32b and 33b service the odd-numbered columns. The columns 15 are not shown for ease of illustration.
The sensing and reference capacitors 32 and 33 in this embodiment are formed from two different layers of polycrystalline silicon (“poly 2” over “poly 1”), with the poly 1 plate formed with a slightly larger area to allow contact to be easily made from overlying metal layers (e.g., the columns 15; not shown) to the bottom capacitor plate. (Note that this sizing difference between the poly 1 and poly 2 plates of the capacitors 32 and 33 is in reality quite small, and that the difference is greatly exaggerated in the Figures). As one skilled in the art of semiconductor processing will understand, a dielectric layer (such as a silicon oxide or silicon nitride) intervenes between the two capacitor plates.
Although the layout of FIG. 3 is not drawn to scale, one of skill in the art will appreciate that the CSH circuitry 18 takes up significant layout space on the imager integrated circuit. This is primarily due to the size of the sampling and reference capacitors 32 and 33. For proper sensing, it is simply the case that the capacitance of these capacitors needs to be quite large (perhaps 1.2 pF a piece). As a result, these capacitors 32 and 33 are made large in area to maximize their capacitance. Thus, even when the sampling and reference capacitors 32 and 33 are split between the top and bottom of the array 12 as shown in FIG. 3, the result is that the CSH circuitry 18 is quite long, what is referred to herein as the “column height” (CH) of the CSH circuitry 18. As can be seen in FIG. 3, this column height CH is dominated by the height h of each of the sampling and reference capacitors 32 and 33. Moreover, further adding to the column height are smaller spaces of dimension d, what is referred to herein as the intercapacitor spacing. These spaces d perform the function of isolating the capacitors 32 and 33, and is usually set as a design constraint. Additionally, the intercapacitor spacing d can also provide the location of other circuitry used within the CSH circuitry 18, such as the selection and column decode transistors 19 and 21 (FIG. 2).
In any event, the column height of the CSH circuitry 18 in CMOS imagers is a significant issue, and reduction of the height is greatly desired. Without schemes to reduce this height, further miniaturization of these devices (which ultimately increases their profitability) will become increasing difficult.